Debug Module for the NanoRV Processor

This thesis addresses the need for a functional debug module for the 'nanorv' processor, a compact implementation of the open-source RISC-V instruction set. The growing adoption of RISC-V across academia and industry highlights the critical role of robust debugging infrastructure in embedded system development, especially for minimalist architectures where traditional debugging methods may not apply. The primary objective of this work is to design, implement, and validate a debug module for the nanorv processor. The module will comply with the RISC-V Debug Specification and be compatible with standard debugging tools via the JTAG interface. Essential functionalities, such as halting, resuming, and single-stepping the processor, will be supported. The methodology involves several key steps: analyzing the specific debug requirements of a simple processor like nanorv, designing a dedicated hardware-based module to interact with the processor's internal state, implementing communication interfaces with both the processor core and external tools, and finally, validating the entire system through simulations and practical testing. The successful outcome of this thesis will not only provide a much-needed, non-intrusive debug solution for the nanorv processor but will also offer a reusable blueprint for future applications involving similar lightweight processors.