Kannamangalam Aslam Basha, Athar Zafeer
(2024)
Automatic insertion of fault-injectable flip-flops in FPGA emulators of satellite computing platforms.
[Laurea magistrale], Università di Bologna, Corso di Studio in
Ingegneria elettronica [LM-DM270]
Documenti full-text disponibili:
Abstract
In space exploration, the demand for electronic processors capable of demonstrating
reliability in the harsh space environment has significantly increased. One of the main
concerns for processors operating in space is their susceptibility to faults induced by
radiation. High-energy particles striking any part of the processor may induce data errors. Traditional approaches, such as radiation hardening, encounter substantial challenges, including high costs and limitations in fabrication. The use of Commercially
Off-The-Shelf (COTS) processors presents a potential solution. Recent advances have
made Commercial Off-The-Shelf (COTS) processors widely accessible, offering speed
and cost-efficiency. However, these generic COTS processors lack reliability features
and are not tested for space applications. In addressing this, our approach integrates
a fault injector module within a scalable processing platform, offering a tool that can
be applied in early design phases. This facilitates validation against various faults,
identifying vulnerable design areas, and enhancing overall system robustness without
being limited to a specific architecture. This enables the simulation and evaluation of
radiation-induced faults, notably single-event errors and stuck-at faults. While we utilize the PULP architecture as a test platform for our module, the applicability extends
to a broader range of architectures. By assessing the fault tolerance of these processors,
this research aims to pioneer a methodology for enhancing their reliability for space
applications. Moreover, our tool provides insights into the parts of the design that are
more sensitive than others, allowing us to identify areas requiring improvement to ensure reliability in space missions. This study demonstrates the potential for adapting
COTS processors to space exploration, marking a shift towards more cost-effective and
technologically advanced solutions viable for critical space-borne applications.
Abstract
In space exploration, the demand for electronic processors capable of demonstrating
reliability in the harsh space environment has significantly increased. One of the main
concerns for processors operating in space is their susceptibility to faults induced by
radiation. High-energy particles striking any part of the processor may induce data errors. Traditional approaches, such as radiation hardening, encounter substantial challenges, including high costs and limitations in fabrication. The use of Commercially
Off-The-Shelf (COTS) processors presents a potential solution. Recent advances have
made Commercial Off-The-Shelf (COTS) processors widely accessible, offering speed
and cost-efficiency. However, these generic COTS processors lack reliability features
and are not tested for space applications. In addressing this, our approach integrates
a fault injector module within a scalable processing platform, offering a tool that can
be applied in early design phases. This facilitates validation against various faults,
identifying vulnerable design areas, and enhancing overall system robustness without
being limited to a specific architecture. This enables the simulation and evaluation of
radiation-induced faults, notably single-event errors and stuck-at faults. While we utilize the PULP architecture as a test platform for our module, the applicability extends
to a broader range of architectures. By assessing the fault tolerance of these processors,
this research aims to pioneer a methodology for enhancing their reliability for space
applications. Moreover, our tool provides insights into the parts of the design that are
more sensitive than others, allowing us to identify areas requiring improvement to ensure reliability in space missions. This study demonstrates the potential for adapting
COTS processors to space exploration, marking a shift towards more cost-effective and
technologically advanced solutions viable for critical space-borne applications.
Tipologia del documento
Tesi di laurea
(Laurea magistrale)
Autore della tesi
Kannamangalam Aslam Basha, Athar Zafeer
Relatore della tesi
Correlatore della tesi
Scuola
Corso di studio
Indirizzo
CURRICULUM ELECTRONICS FOR INTELLIGENT SYSTEMS, BIG-DATA AND INTERNET OF THINGS
Ordinamento Cds
DM270
Parole chiave
FPGA,faults,resilience,testing,faultinjectormodule,TCL,scripts,Single Event
Data di discussione della Tesi
18 Marzo 2024
URI
Altri metadati
Tipologia del documento
Tesi di laurea
(NON SPECIFICATO)
Autore della tesi
Kannamangalam Aslam Basha, Athar Zafeer
Relatore della tesi
Correlatore della tesi
Scuola
Corso di studio
Indirizzo
CURRICULUM ELECTRONICS FOR INTELLIGENT SYSTEMS, BIG-DATA AND INTERNET OF THINGS
Ordinamento Cds
DM270
Parole chiave
FPGA,faults,resilience,testing,faultinjectormodule,TCL,scripts,Single Event
Data di discussione della Tesi
18 Marzo 2024
URI
Statistica sui download
Gestione del documento: