Efficient Trace for RISC-V: Design, Evaluation, and Integration on a CVA6 multicore design

n modern CPUs, understanding program behavior is essential for effective code debugging and performance analysis. However, commonly used techniques are often invasive and may alter program execution by introducing stalls and exceptions. To address this, CPU vendors have developed less intrusive methods for code monitoring, known as tracing. Tracing encompasses a set of techniques for capturing various types of runtime information from the system. Among these, Branch Tracing specifically analyzes the individual instructions executed by the CPU, focusing only on reporting code discontinuities. Each branch tracing standard is tailored to its target Instruction Set Architecture (ISA). Within the open-source RISC-V standard, a non-ISA-specific branch tracing specification has been developed and ratified, called the Efficient Trace Specification. This specification outlines the design rules and packet formats required for implementing Branch Tracing on a RISC-V core. The contributions of this thesis are i) The design and testing of a Trace Encoder compliant with the Efficient Trace Specification. ii) The integration of this Trace Encoder into a state-of-the-art RISC-V System-on-Chip emulated on FPGA featuring a dual-core host domain. iii) An evaluation of the area overhead and performance introduced by the Trace Encoder. The implemented Trace Encoder introduces an area overhead of 4.15% relative to the Ariane core and achieves an average compression rate of 95.07% on relevant platform benchmarks.