Analysis of High-Level Injection in SCR-LDMOS for Enhanced ESD Protection of Smart Power Technology

The protection of Integrated Circuits (ICs) against Electrostatic Discharges (ESD) is becoming increasingly important due to the progressive reduction of robustness of these circuits against high current surges from ESD events, as a consequence of technology scaling. A commonly implemented self-protected device is the Silicon Controlled Rectifier - Lateral Double-Diffused Metal-Oxide-Semiconductor (SCR-LDMOS), which combines the output driver capabilities of the LDMOS with the ESD robustness of the SCR. The introduction of Smart Power Technology in different application domains, such as automotive, poses an increase in the challenge of ESD protection, due to the higher power supply voltages characterizing this technology. Indeed, a high holding voltage in the protection devices is crucial to mitigate the risk of latch-up. In this thesis, different SCR-LDMOS structures based on Texas Instruments LBC9 technology have been simulated using Synopsys Sentaurus TCAD. In particular, the effect of high-level injection on the holding voltage and failure current has been investigated. A layout-only optimization for increased holding voltage has been proposed for effective protection of Smart Power Technology.