Integration of a digital in-memory computing accelerator into a RISC-V vector processor through integrated matrix ISA extensions

This thesis investigates architectural approaches for integrating DIMC with a RISC-V (SPATZ PULP VECTOR PROCESSOR) by extending the RISC-V Vector architecture and incorporating concepts from the Integrated Matrix Extension (IME). The research begins with a comprehensive design space exploration that evaluates different architectural choices, including DIMC data mapping strategies, and various coupling mechanisms between the processor and the memory-compute units. These design alternatives were analyzed based on performance metrics such as latency, throughput, and hardware area efficiency. To enable efficient matrix-oriented computations commonly used in deep learning workloads, the proposed architecture supports IME-inspired inner matrix execution mechanisms, where matrix tiles are processed through optimized inner loops to maximize data reuse and computational throughput. In addition, a set of custom instructions was introduced to facilitate communication between the RISC-V vector processor and the DIMC accelerator, enabling efficient configuration, execution control,data loading, and result retrieval. The system integrates an the processor and the DIMC arrays. This manages command decoding, buffering mechanisms, and synchronization between vector operations and in-memory computations. Dedicated buffering structures and FIFO-based data paths were designed to support efficient data streaming and to minimize latency during matrix operations. The resulting architecture demonstrates how combining DIMC with IME-based matrix execution and RISC-V vector extensions can significantly improve the efficiency of deep learning computations on edge devices. Building comparison among IME and custom instruction with their defined pron and cons.