FPGA implementation of a model predictive control for neutral-point clamped converters

Since the early 2000s, Model Predictive Control (MPC) has been successfully applied to power electronic converters, with particular focus on Finite-Control-Set MPC (FCS-MPC). This approach, which directly generates the control signals for the switches, enables the use of optimality criteria better suited to handling the discrete nature of converters. Initially, the resolution of the optimization problem relied on a full enumeration of the control set. However, since 2014, a more efficient branch-and-bound technique, known as the Sphere Decoding Algorithm (SDA), has been introduced. This method allows for the optimization of significantly more complex problems, expanding the control set from a few dozen elements to several million. Computational power remains a critical factor in the implementation of an effective control system, as it determines the feasible prediction horizon length, system complexity, and sampling frequency. In the literature, dedicated computational systems have been developed for solving the FCS-MPC optimization problem, proving to be effective but with room for improvement in terms of efficiency. This thesis proposes an architecture for an FCS-MPC controller based on SDA, using as a case study the current control of a three-phase RL load through a five-level Neutral-Point Clamped (NPC) converter. The controller has been implemented on a System-on-Chip (SoC) and validated using the Hardware-in-the-Loop (HIL) methodology, simulating both the load and the converter on the SoC itself. Finally, the proposed architecture has been compared with one of the most high-performance solutions in the literature, demonstrating a comparable resource usage but a computational power at least 15 times higher.