Performance and Robustness of low-voltage enhancement-mode GaN-based power HEMTs with p-type gate

This thesis is a report of the work of a six-months internship in imec, a R&D hub for nano- and digital technologies based in Leuven, Belgium. During this internship I worked on the characterization of enhancement-mode GaN-based lateral HEMT devices with p-GaN gate, aiming to understand the impact of different process variations, device layout and architecture on the electrical performance and reliability of the devices. After the first essential steps that included the study of the basics about device structure, fabrication and operations and literature review, I started to plan experiments and characterization routines with a focus on gate and OFF-state reliability and I performed the measurements and the data elaboration. The first chapter of this elaborate will present an overview on the field of power electronics: its relation to the theme of climate change and the state of its market nowadays. Then a presentation of p-GaN HEMT devices will follow, explaining the working of the transistor and all its fabrication options and issues. After that, the report will get into the real work done during the internship: two chapters will explain all the experimental details of the measurements and present the obtained results and observations. A final chapter will in the end summarize the results and draw some conclusions.