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Abstract
Nowadays, there is an increasing need to develop, reliable and low-cost power devices able to withstand high voltage drops and currents during the off-state and on-state operation, respectively. A useful strategy is represented by the integration on-chip of power devices with CMOS logic and analog technologies. This kind of solution is named BCD (BIPOLAR-CMOS-DMOS) technology.
One of the fundamental power device on which the BCD technology is based is the LDMOS (Laterally-Diffused Metal-Oxide Semiconductor) transistor. The study and understanding of the degradation mechanisms affecting their long-term reliability is of great interest because of the stringent requirements in terms of safety, robustness, etc., basing on the field of application of the circuit in which the devices are integrated.
This work, in collaboration with STMicroelectronics, focuses on the optimization of the p-channel LDMOS transistors and aims at studying and understanding how the Hot Carrier Stress (HCS) degradation impacts their performance for long working times. The behavior of the device is simulated through the Sentaurus TCAD where a HCS degradation model is employed to understand which are the dominant effects of the hot particles within the semiconductor, applying stress conditions aimed at accelerating the degradation mechanisms causing the drift of key parameters.
In this work the focus is on the on-resistance, since it results to be the main parameter affected by degradation. The goal is to understand exactly which is the main cause of such variation in order to be able to allow a technology improvement. The simulations have been calibrated against experimental data.
The on-resistance curve are correctly calibrated under certain stress conditions. The goal of the thesis activity has been achieved with accurate results, bringing to a more detailed description of a p-channel LDMOS power device through the development of a first version of the predictive simulation tool.
Abstract
Nowadays, there is an increasing need to develop, reliable and low-cost power devices able to withstand high voltage drops and currents during the off-state and on-state operation, respectively. A useful strategy is represented by the integration on-chip of power devices with CMOS logic and analog technologies. This kind of solution is named BCD (BIPOLAR-CMOS-DMOS) technology.
One of the fundamental power device on which the BCD technology is based is the LDMOS (Laterally-Diffused Metal-Oxide Semiconductor) transistor. The study and understanding of the degradation mechanisms affecting their long-term reliability is of great interest because of the stringent requirements in terms of safety, robustness, etc., basing on the field of application of the circuit in which the devices are integrated.
This work, in collaboration with STMicroelectronics, focuses on the optimization of the p-channel LDMOS transistors and aims at studying and understanding how the Hot Carrier Stress (HCS) degradation impacts their performance for long working times. The behavior of the device is simulated through the Sentaurus TCAD where a HCS degradation model is employed to understand which are the dominant effects of the hot particles within the semiconductor, applying stress conditions aimed at accelerating the degradation mechanisms causing the drift of key parameters.
In this work the focus is on the on-resistance, since it results to be the main parameter affected by degradation. The goal is to understand exactly which is the main cause of such variation in order to be able to allow a technology improvement. The simulations have been calibrated against experimental data.
The on-resistance curve are correctly calibrated under certain stress conditions. The goal of the thesis activity has been achieved with accurate results, bringing to a more detailed description of a p-channel LDMOS power device through the development of a first version of the predictive simulation tool.
Tipologia del documento
Tesi di laurea
(Laurea magistrale)
Autore della tesi
Mazzoli, Andrea
Relatore della tesi
Correlatore della tesi
Scuola
Corso di studio
Ordinamento Cds
DM270
Parole chiave
LDMOS,TCAD,Sentaurus,HCS degradation,on-resistance,BCD technology,p-channel
Data di discussione della Tesi
10 Marzo 2021
URI
Altri metadati
Tipologia del documento
Tesi di laurea
(NON SPECIFICATO)
Autore della tesi
Mazzoli, Andrea
Relatore della tesi
Correlatore della tesi
Scuola
Corso di studio
Ordinamento Cds
DM270
Parole chiave
LDMOS,TCAD,Sentaurus,HCS degradation,on-resistance,BCD technology,p-channel
Data di discussione della Tesi
10 Marzo 2021
URI
Gestione del documento: