Data-Dependent Power Characterization of a Matrix Multiplication Unit

This master’s thesis presents an integrated framework for the energy characterization of a high-performance RISC-V hardware accelerator, hereafter referred to as the MMU (Matrix Multiplication Unit), optimized for matrix operations in Deep Learning. The research addresses the critical challenge of estimating power consumption in advanced CMOS technology, where power is primarily driven by switching activity generated by the statistical properties of real-world input data. The methodology follows a rigorous three-phase data reduction pipeline. In Phase I, a deterministic extraction flow captures actual AI workloads from Llama 3.2-1B and ResNet-50, generating a baseline of 20,000 tile combinations. This pool is then refined through Quantile Stratified Sampling to a representative subset of 500 samples, ensuring statistical coverage of the sparsity spectrum while overcoming simulation time constraints. In Phase II, an automated orchestration layer processes these 500 testbenches through gate-level simulations using industry-standard tools. Finally, in Phase III, the resulting power data is analyzed via K-Means clustering to identify 50 “medoids” (the Golden Set) representing the most informative energy states of the hardware. This multi-stage approach provides a high-fidelity, permanent benchmark for power regression monitoring and establishes a robust dataset for the training of future power-predictive surrogate models, bridging the gap between architectural level deep learning specifications and physical gate-level implementation.