Feasibility study and emulation of the Hough Transform algorithm on FPGA devices for ATLAS Phase-II trigger upgrade

Levrini, Giacomo (2020) Feasibility study and emulation of the Hough Transform algorithm on FPGA devices for ATLAS Phase-II trigger upgrade. [Laurea magistrale], Università di Bologna, Corso di Studio in Physics [LM-DM270]
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In the next 10 years, a radical upgrade is expected for the Large Hadron Collider focused in achieving the highest values in the instantaneous and integrated luminosity. Both the subdetectrors of the experiments and their data acquisition systems will need an upgrade. For the Phase-II upgrade of the Trigger and Data Acquisition System (TDAQ) of the ATLAS experiment a common platform has been created to share the common firmware, software and tools that are ongoing and that will come in the next years within the ATLAS TDAQ collaboration. The environment includes a set of design procedures, a virtual machine as repository for the firmware and some automatic tools for the continuous integration and versioning. The platform is under testing, as the firmware will be tested on the TDAQ upgraded, it will also be used for the prototype cards that will be produced as demonstrator for the ATLAS Hardware Tracking for the Trigger (HTT) system. For the HTT project a physical environment is being prepared, exploiting Peripheral Component Interconnect express (PCIe) and ACTA crates. My personal work has been the design of a part of track-fitting algorithms, in particular the one using the Hough Transform. This implementation has been required by the ATLAS experiment as an alternative solution to the baseline proposal accepted and described in the TDAQ Upgrade Technical Design Report (TDR). I have developed and tested a set of pattern vectors used not only in the simulation and validation of the algorithm, but also in the hadware integration on a FPGA based hardware accelerator. The used technology is based on high-performance Xilinx Ultrascale+ FPGA, implemented on VCU1525 board. This work is going to be validated by the ATLAS collaboration very soon, so to understand how we can proceed in the future upgrade. Bologna is the only Italian institute which participates in the integration of a tracking algorithm in the ATLAS trigger upgrade, using high performance FPGA-based hardware.

Tipologia del documento
Tesi di laurea (Laurea magistrale)
Autore della tesi
Levrini, Giacomo
Relatore della tesi
Correlatore della tesi
Corso di studio
Ordinamento Cds
Parole chiave
ALTAS,FPGA,Hardware accelerator,TDAQ,Trigger,Hough Transform,HTT
Data di discussione della Tesi
11 Dicembre 2020

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