Development of a PicoTDC-based card for the ALICE TOF detector

The readout electronic system related to the ALICE TOF (Time-Of-Flight) uses the TRM (TDC readout module) card, based on the HPTDC (High-Performance TDC) ASICs, as the main element to provide the time measurements of a particle crossing the TOF detector. This master thesis is linked to the wider project of a new TRM2 board, begun since the TRM board components are now out of production and the TOF readout system must be reliable during the current and the next LHC Runs. The thesis focuses on the development of a test board hosting a PolarFire FPGA and two PicoTDC ASICs, which are the main components selected for the TRM2 development. The work done regards the control and test of the PicoTDCs configuration and readout, through the design of the FPGA firmware architecture and the related software routines. As the board supports Ethernet connection with the FPGA, the firmware and software were built considering the IPbus protocol, which communicates over the Ethernet exploiting the UDP/IP model. The IPbus is implemented on the FPGA as a master-slave structure, in which the IPbus slaves implement different hardware features that can be controlled through IPbus data transfers. The designed firmware relies on a structure that implements a 1Gb/s Ethernet communication able to manage the PicoTDCs and the board features. Then dedicated software front-end libraries were built to control the operations of each slave. The whole system was used to test the setup for a PicoTDC resolution measurement, employing a programmable delay line with a 0.5 ps resolution. The firmware and software developed proved reliable during all 36 hours of measurement, providing 18 datasets of 10^7 events each. Furthermore, the analysis showed excellent compatibility between the measured time differences and the configured time delays. A single channel resolution of (2.95±0.43) ps was estimated for both the PicoTDC ASICs.