Early Power Consumption Estimation in Digital Design Flow

Concepts such as efficiency, reliability, and portability are only made possible by the constant evolution of modern technological processes related to the microelectronics industry. With the increasing market demand for portable devices, the need for high power efficiency and long-llife battery-powered devices is becoming a prominent issue, making power analysis a relevant step in the design of these devices. While the reduction in device size has led to considerable advantages in terms of integration and performance, on the other hand it has emphasizes problems, such as power consumption and heat dissipation. In fact, the size scaling of device allows to work at higher frequencies, affecting the dynamic component of power. Before tapeout, the most accurate estimations of a device's power consumption are available only in the final stages of the design process, the stages that define its closure. The challenge that designers and especially CAD teams are facing today is to reconcile the accuracy and availability of these results: in fact, some details of implementations, which make the analyses accurate, are not yet available in the primordial stages, making potential analyses less accurate. This thesis presents an in-depth exploration of Power Analysis methodologies in the Sign-Off stage, emphasizing the benefits of adopting the Delay Shifting Algorithm and analyzing the impact of glitches on power consumption. Additionally, it introduces an Early Power Analysis methodology that enhances power estimation accuracy and enables power-aware design decisions at early design stages. By combining advanced techniques and promoting early power-awareness, the proposed methodologies contribute to the development of energy-efficient digital integrated circuits, ultimately benefiting the overall electronic system design process.