Analysis and simulations of Hot-Carrrier Injection in Field-Plate p-channel devices in BCD110AP Smart Power Technology

The increasing demand for smart electronic systems that has been taking place for some years resulted in the need of both low (CMOS/BiCMOS) and high-voltage (Smart Power) devices. Moreover, devices must be performant, reliable, low-cost and capable to withstand high voltage and drive large amount of current in on-state operation regime. Devices should be integrated in unique chip (SoC) in order to obtain better performances: miniaturization would reduce power consumption and grants cost effectiveness. Smart Power integrated technologies incorporate analog Bipolar Junction Transistor (BJT), low-voltage logic Complementary Metal Oxide Semiconductor (CMOS) and high-voltage switches Double Diffused MOS (DMOS or drift MOS, dMOS) into a single silicon chip with a technology called Bipolar-CMOS-DMOS (BCD). Thanks to their compatibility with the standard CMOS, DMOSFETs are the best choice for high-voltage switching applications. Because of their range of voltage biases, they mostly suffer for degradation phenomena due to hot-carrier injection (HCI) and hot-carrier stress (HCS), causing instability over long time periods and limiting their operating lifetime. It is thus of interest to investigate these phenomena. In this thesis, carried out in collaboration with STMicroelectronics, High-Voltage p-channel transistors specifically designed for the study of HCI and gate-current degradation in BCD technology have been investigated. Devices were characterized in the STMicroelectronics laboratory and numerically simulated in the framework of the Sentaurus Technology Computer Aided Design (TCAD) software by Synopsys. The goal was to reproduce the behavior of the transistors in order to understand the way and to what extent, the HCI impacts on gate and drain currents in the linear and the saturation regimes, as well as during a stress time period.