FPGA-based hardware demonstrator of a Hough transform pattern recognition algorithm for the ATLAS Phase-II trigger upgrade

This Master Thesis discusses the Phase-II upgrade of the Trigger and Data Acquisition system of the detector called A Toroidal LHC ApparatuS (ATLAS). An R&D program, which has included the creation of two task forces, was launched in the 2021 Spring with the aim to produce one engineered solution for the track reconstruction at the Event Filter (EF) level. The Electronic group of the University of Bologna is taking part in the proposal of the heterogeneous commodity task force, which consists of the previous project called Hardware Tracking for the Trigger. The heterogeneous solution is based on a mixed commodity platform of classic processors and accelerators, where track reconstruction is expected to be performed via the use of mathematical functions, for example through the implementation of Hough Transform algorithm on the FPGA which will be part of the EF of ATLAS Phase-II. The R&D activities performed until now include the development of the firmware for the HT. Final goal of this Master Thesis is the creation of a hardware demonstrator able to test the ongoing firmware design. To fulfill this purpose, a new firmware architecture is exploited and it relies on a manageable Peripheral Component Interconnect Express transmission. The integration of the two firmware designs is realized with the development of a two first-in-first-out structure. In this way it is demonstrated the correct implementation of the ongoing Hough Transform firmware design.