Quality investigation of an ATLAS Phase-II DAQ board via Signal Integrity simulations

The Large Hadron Collider (LHC) is the most significant expression of the efforts of physicists all over the world and it is always under development to push its colliding and detection limits. As a matter of fact, by the end of 2024 the installation work of a renewed collider, capable of reaching a nominal luminosity of 7.5x10^34 cm-2*s-1, will take place. The new apparatus, called High Luminosity-LHC (HL-LHC), will be operational at least for another decade and, to accomplish the challenges posed by the search for new physics, the main detectors such as A Toroidal LHC ApparuS (ATLAS) and Compact Muon Solenoid (CMS) will be upgraded for Phase-II. Together with the structural changings in ATLAS sub-detectors, the entire Trigger and Data Acquisition (TDAQ) strategy will be upgraded by the implementation of new technologies. Among these technology advancements the FrontEnd LInk eXchange (FELIX) DAQ board, developed by Brookhaven National Laboratory (BNL) together with ATLAS, will play a prominent role. The new high-speed Printed Circuit Board (PCB) will handle the communication between the sub-detectors, the first level of trigger and the Dataflow, thanks to its multi Gb/s links and programmable logic, which makes the board a versatile and long-lasting element of the TDAQ chain. My personal work has been testing some of the transmission channels of FELIX Phase-II board, in the light of Signal Integrity (SI), with the goal to supply simulation results confirming the reliability of its high data-rate lines. Ultimately, I have given evidence that high-speed digital design is a key step in DAQ boards research and development, and it is an essential instrument to reach optimal performances.