Boundary-scan for High-speed Serial Links

The complexity of integrated circuit (IC) designs continues to increase with the constant advancement of process technology and decrease of feature size in a relentless effort to achieve better performance and reach new milestones. However, with the increasing density and complexity comes a higher probability of defects occurring as well as a higher impact of these defects on the overall performance. Testing, thus, proves essential in order to guarantee defect-free designs. Effective and efficient testing in terms of both cost and time becomes essential as well because of the continually rising cost of testing. Abstract Serializer-deserializer (SerDes) devices or serial-link transceivers, which represent the device-under-test (DUT) in this thesis, are no different. Since the interface is the bottleneck in the performance of various systems, efforts continue to push for faster, smaller, and more power-efficient SerDes, leaving it with stringent specifications to meet. This leads to it being susceptible to the higher defect probability we just mentioned. As these are wireline transceivers, the robustness of the interconnects is especially critical. These defects that affect the interconnects are troublesome due to the fact that it is relatively easy for the fault to be masked which would indicate a non-existent fault within the design itself. In this thesis, we propose a test receiver that is capable of putting the interconnects under test in both DC-coupled and AC-coupled scenarios in compliance with the IEEE-1149.1 and IEEE-1149.6 standards.